This invention relates to a complementary metal-oxide-semiconductor (CMOS) memory device such as a dynamic random access memory (RAM), more particularly to a CMOS memory device with improved sense amplifier biasing.
A CMOS device is formed on a substrate of one conductive type having wells or tubs of the opposite conductive type: for example, on a p-type substrate having n-type wells (hereinafter referred to as n-wells). In the device, p-channel metal-oxide-semiconductor (PMOS) transistors are disposed in the n-wells and n-channel metal-oxide-semiconductor (NMOS) transistors are disposed in the p-type substrate outside the n-wells, forming a complementary structure with well-known advantages of low power dissipation.
A CMOS memory device generally has p-channel and n-channel sense amplifiers to amplify data read from the memory cells of the device onto bit lines. Sense amplifiers of one channel type are disposed in wells of the opposite conductive type: for example, p-channel sense amplifiers are disposed in n-wells. The wells are biased to prevent short-circuiting of the power supply, a potentially destructive phenomenon known as latch-up. Prior-art designs use power lines for biasing the wells.
One disadvantage of this scheme is that power lines are subject to voltage fluctuations caused, for example, by variations in the supply voltage, and are also susceptible to voltage drops due to the impedance of the power lines. Such voltage fluctuations and drops can activate parasitic transistors in the well structures, leading to latch-up.
With reference to FIG. 1, for example, a prior-art sense amplifier comprises a pair of PMOS transistors 2 connected to bit lines BL and BL disposed in an n-well 4 in a p-type substrate 6. The sense amplifier is driven by a signal denoted PS which is supplied to the sources 8 of the transistors 2. The n-well 4 is biased by a pair of contacts 10 and 11 connected to power lines VN. Outside the n-well, as part of an adjacent circuit, is a ground contact 12 connected to a ground line Vss.
If a large drop occurs in the VN voltage, parasitic bipolar transistors 14 and 15 in the n-well may turn on, so that when the PS signal is activated a current i1 flows from the source 8 of the PMOS transistors 2 to the p-type substrate 6. Current from the parasitic transistor 15 turns on another parasitic transistor 16 connecting the power contact 11 to the ground contact 12. The power supply is then short circuited; current i2 flows directly from the VN line to ground; latch-up has occurred.
Another disadvantage of this scheme is that the extra required power lines take up space, leading to undesirably large chip size. FIGS. 2A and 2B, for example, show two typical layouts of the VN bias power lines. In FIG. 2A a main bias power line VNa from a power pad 18 feeds a plurality of lines VN that bias the wells of sense amplifiers 20.sub.1 to 20.sub.n. In FIG. 2B there are two main power lines VNa and VNb for feeding bias power to both ends of the biasing lines VN. The lines VNa and VNb are used solely for biasing; they do not supply operating power to any circuits. The need to provide such power lines constrains memory design and reduces the space available for memory cells. In FIG. 2B the power line VNb crosses the signal lines PS.sub.1 to PS.sub.n by which sense amplifier drive circuits 22.sub.1 to 22.sub.n drive the sense amplifiers 20.sub.1 to 20.sub.n. Accordingly, the line VNb and the lines PS.sub.1 to PS.sub.n must be routed in different metal layers, further constraining the circuit design.
With reference to FIGS. 2C and 2D, some prior-art designs attempt to conserve space by using the same power line VNa or lines VNa and VNb both to bias sense-amplifier wells and to supply power to peripheral circuits 24 in the device. Unfortunately, such designs tend to give rise to increased impedance on the power lines, reducing the voltage supplied to the peripheral circuits 24, so that they do not always operate reliably.